1. Field of Invention
The present invention relates to an analog integrated circuit technology, and more particularly to a low dropout regulator circuit without external capacitors rapidly responding to load change.
2. Description of Related Arts
The low dropout regulator (LDO) is widely used in various analog integrated circuits and mixed-signal integrated circuits owing to its advantages of low output voltage ripple, low noise and low quiescent current.
A conventional LDO circuit is shown in FIG. 1, wherein VREF_GEN is a reference voltage generating circuit, OP is an operational amplifier, MP1 is an output regulating transistor, RF1 and RF2 are feedback resistors, RL is a load resistor, CL is a load capacitor. The working principle of the LDO is described as follows. The reference voltage generating circuit transmits a reference voltage to a negative input node of the operational amplifier, then the feedback resistors feedback a voltage in proportion to the output voltage to a positive input node of the operational amplifier, and then the operational amplifier detects the difference between the feedback voltage and the reference voltage. According to the difference, the gate voltage of the output regulating transistor MP1 is regulated. When the feedback voltage VFB is higher than the reference voltage VREF, the operational amplifier will pull up the gate voltage Vc of the output regulating transistor, then the output voltage VOUT will be decreased so as to lower the feedback voltage VFB to the reference voltage VREF. When the feedback voltage VFB is lower than the reference voltage VREF, the operational amplifier will pull down the gate voltage Vc of the output regulating transistor, then the output voltage VOUT will be increased so as to increase the feedback voltage VFB to the reference voltage VREF. Therefore, the LDO circuit stabilizes the output voltage VOUT by the negative feedback of the operational amplifier and the regulating transistor. When the LDO circuit is stable, the output voltage thereof can be expressed as follows:VOUT=VREF*(RF1+RF2)/RF2
For the LDO circuit shown in FIG. 1, when the rapid load transition (ns level) occurs, the transient current what are needed herein is mainly provided by the load capacitor CL for obtaining the stable output voltage. Therefore, it is necessary for the LDO circuit to be provided with a more than μF-level large capacitor by the exterior so as to provide a good load transient response thus increasing the system cost. Furthermore, the resistance of the external capacitor's parasitic resistor will affect the loop stability of the LDO circuit, thus greatly increasing the complexity of the system design. If there is no external capacitor CL, when the rapid load transition (ns level) occurs, it has to be the negative feedback loop to respond to the load transition, so it is required that the bandwidth of the whole loop is larger than GHz. The output regulating transistor MP1 has a very large width-length ratio and a large gate parasitic capacitance, so the current of the operational amplifier must be very large for obtaining the GHz-level loop bandwidth, otherwise the deficiency of the loop bandwidth will cause the big ripple of the output voltage VOUT. When the ripple of the output voltage VOUT exceeds ±10%, the LDO power supply system will not work properly.